This invention relates generally to telephone communication systems and more particularly to circuitry for synthesizing and monitoring clock signals for use in such systems.
As is known in the art, telephone communication systems currently operate in a variety of formats, such as T1 format (North American format) or Conference of European Postal and Telecommunications Administration (CEPT) format (European format). These formats indicate, inter alia, the frequency at which voice and/or data information is transmitted. For example, in CEPT telecommunication systems, the transmission frequency is 2.048 MHz; whereas, T1 transmission occurs at a frequency of 1.544 MHz.
As is also known in the art, in such telephone communication systems, often a reference clock signal is used to synthesize additional clock signals having frequencies which are integer multiples of the frequency of the reference clock signal. For example, in a T1 format telephone communication system, conventionally an 8 KHz reference clock signal provides the sampling rate for voice and/or data sampling and feeds a clock signal synthesizing circuit, such circuit synthesizing additional clock signals, or frequency synthesized output signals, having frequencies such as 64 KHz and 1.544 MHz, for example, for use in other parts of the system.
One method known in the art for generating a plurality of frequency synthesized signals, having frequencies which are integer multiples of the frequency of a reference clock signal, is to use a phase-locked loop circuit and a divider circuit. More particularly, the phase-locked loop circuit provides, at an output thereof, a signal which has a known phase relationship relative to the reference clock signal fed thereto. The output of the phase-locked loop circuit is, generally, fed to a divider circuit having a plurality of internal dividers corresponding to different divisor factors. The plurality of frequency synthesized output signals are, thus, provided at a plurality of outputs of the divider circuit.
As is also known in the art, it is often desirable to monitor a characteristic of an electrical signal. For example, it may be desirable to monitor a characteristic of the reference clock signal fed to a frequency synthesizing circuit, or of a frequency synthesized output signal. One method known in the art for monitoring the presence or absence of a signal is to use a comparator circuit. This type of circuit compares a fixed reference, or threshold level voltage with the voltage of a monitored signal and provides a logic signal output representative of the relative levels of the voltages being compared. More particularly, a comparator circuit indicates whether the voltage level of the monitored electrical signal is above or below that of the fixed reference, or threshold level voltage. Thus, in such an application, the comparator circuit is used to indicate whether the monitored signal is present (i.e. for example, when the voltage of the monitored signal is greater than the voltage of the fixed reference, or threshold level voltage) or absent (i.e. for example, when the voltage of the monitored signal is less than the voltage of the threshold level voltage). Such a comparator circuit may be adequate in certain applications, however, it is often desirable to monitor the frequency characteristic of an electrical signal in order to determine whether the signal has drifted away from its nominal frequency or whether, due to a failure in the circuitry, the frequency of the electrical signal is different than the desired frequency.
Two typical sources of error associated with a frequency synthesizing circuit are an error in the frequency of the reference clock signal or an error, or failure, in the operation of the circuit itself (i.e. either the phase-locked loop circuit or the divider circuit). An error in the frequency of the reference clock signal can be detected by monitoring the frequency of such signal; whereas, an error in the operation of the signal synthesizing circuitry manifests itself as an error in the frequency of the synthesized output signals and, thus, can be detected by monitoring the frequency of such signals.
One method known in the art for monitoring the frequency of a reference clock signal is to utilize, in generating the frequency synthesized output signals, a phase-locked loop circuit having a lock detection feature. An example of such a phase-locked loop circuit is Part No. 74HC7046 manufactured by RCA Corporation, Solid State Division of Somerville, N.J. Such a phase-locked loop circuit provides a logic signal indicating the presence or absence of an error in the frequency of the reference clock signal fed thereto. This feature is particularly desirable, in applications, in which an alternate, or secondary, reference clock signal is available for coupling to the clock signal synthesizing circuit in the event that an error is detected in the original, or primary, reference clock signal itself. In other words, it is desirable to ensure the accuracy of the alternate reference clock signal prior to coupling such alternate signal to the clock signal synthesizing circuit. In such applications, more than one reference clock signal may be coupled to the phase-locked loop circuit through conventional multiplexer circuits. More particularly, the reference clock signals are coupled to inputs of a multiplexer circuit and an output of such circuit is coupled to the phase-locked loop circuit. In response to a control signal, the multiplexer couples a selected one of the reference clock signals to an output thereof and, thus, to the phase-locked loop circuit. In this way, the signal synthesizing circuit may be fed by the alternate reference clock signal in the event of a failure on the primary reference clock signal. While this method may be adequate for monitoring the frequency of one or more reference clock signals, it does not provide any indication of the presence or absence of an error in the frequency of the synthesized output signals produced by the phase-locked loop and divider circuits. Thus, even if the phase-locked loop circuit detects the absence of an error in the frequency of the reference clock signals, there may in fact be an error in the frequency of one or more of the synthesized output signals due a failure within the signal synthesizing circuitry.